The present invention relates to a semiconductor memory device including an on die thermal sensor (ODTS), and more particularly, to an ODTS capable of coping with any specification discussed in an ODTS test group (TG) of a Joint Electron Device Engineering Council (JEDEC) for defining an operating point of the ODTS.
A dynamic random access memory (DRAM) cell includes a transistor for operating as a switch and a capacitor for storing a charge, i.e., data. According to whether the capacitor stores the charge, i.e., whether a terminal voltage of the capacitor is high or low, a logic level of the data is determined as a high level or a low level.
Since the data is stored in the capacitor as an accumulated electrical charge form, ideally, there is no power consumption for the data storage. However, because of a leak current due to a PN junction of a metal oxide semiconductor (MOS) transistor, the stored initial charge may be discharged and, thus, the data may vanish.
To prevent data loss, the data stored in a memory cell is read and the read data is restored into the memory cell by recharging the memory cell with a normal charge before the data vanishes. This operation should be periodically performed in order to maintain data.
The above-mentioned recharging operation is called a refresh operation and, generally, a control of the refresh operation is performed by a DRAM controller. Due to the refresh operation, refresh power is consumed. In case of a battery operated system, which requires lower power consumption, reducing power consumption is very important and is a critical issue.
One method of reducing the power consumption for the refresh operation is changing a refresh period according to temperature. As the temperature decreases, a data holding time of the DRAM is longer. Therefore, by dividing a temperature range into several temperature regions and by lowering a frequency of a refresh clock at a relatively low temperature region, power consumption is reduced.
Accordingly, a device for correctly sensing the temperature of the inside of the DRAM and for adjusting the refresh clock frequency is required.
As a semiconductor unit is highly integrated and is operated at a higher speed, a significant amount of heat is generated. The generated heat increases internal temperature of the semiconductor unit and, thus, can disturb the semiconductor unit from normal operation. The generated heat may cause a defect in the semiconductor unit.
Therefore, a device for correctly sensing the temperature of the semiconductor unit and for outputting the sensed temperature information is needed.
FIG. 1 is a block diagram of a conventional on die thermal sensor (ODTS) for use in a semiconductor memory device.
The conventional ODTS 1 includes a temperature voltage generating unit 2, an analog-to-digital converting unit 3, a code converting unit 4, and an operating controller 5.
The temperature voltage generating unit 2 detects an internal temperature of the semiconductor memory device and generates a temperature voltage VTEMP according to the detected internal temperature. Further, the temperature voltage generating unit 2 outputs maximum and minimum variation voltages VULIMIT and VLLIMIT. The maximum and minimum variation voltages VULIMIT and VLLIMIT are generated from a bandgap circuit provided in the temperature voltage generating unit 2 and keep a constant voltage level in spite of a variation of process, voltage and temperature (PVT). A user can set voltage levels of the maximum and minimum variation voltages VULIMIT and VLLIMIT in response to a virtual fuse code VIRTUAL_FUSE_CODE and an adjusting code TRIM_CODE.
The analog-to-digital converting unit 3 converts the temperature voltage VTEMP into a digital code DIGITAL_CODE having a digital value, and outputs a first update signal UPDATE1 for informing an update of the digital code DIGITAL_CODE when the digital code DIGITAL_CODE is updated according to the internal temperature of the semiconductor memory device. Herein, a voltage level of the digital code DIGITAL_CODE is adjusted between the maximum variation voltage VULIMIT and the minimum variation voltage VLLIMIT. The digital code DIGITAL_CODE is input to the temperature voltage generating unit 2 as the adjusting code TRIM_CODE to thereby adjust the digital code DIGITAL_CODE between the maximum variation voltage VULIMIT and the minimum variation voltage VLLIMIT.
The code converting unit 4 converts the digital code DIGITAL_CODE into a temperature information code TEMP_CODE and a plurality of flag signals TRIP_POINT_FLAG<0:M>, M being a positive integer, to output them with a second update signal UPDATE2 for informing an update of the temperature information code TEMP_CODE when the temperature information code TEMP_CODE is updated according to the internal temperature of the semiconductor memory device.
The operating controller 5 controls an operation on a normal mode of the ODTS 1 based on an enable signal ENABLE, controls an operation on a self-refresh mode of the ODTS 1 based on a self-refresh signal SREF, and controls an operation on a test mode of the ODTS 1 based on a test enable signal TEST_ENABLE. In detail, the operating controller 5 controls an operation of the temperature voltage generating unit 2 by generating a first operating control signal BGR_ON, controls an operation of the analog-to-digital converting unit 3 by generating a second operating control signal ADC_ON, and controls an operation of the ODTS 1 by generating a test mode signal TEST_MODE for controlling the test mode operation.
A multi-purpose register 6 located at outside of the ODTS 1 stores the temperature information code TEMP_CODE in response to the second update signal UPDATE2. The stored temperature information code TEMP_CODE is output to the outside through a data output pad (DQ_PAD) or a memory controller can change a refresh period of the semiconductor memory device by reading the temperature information code TEMP_CODE stored by the multi-purpose register 6.
A self-refresh oscillation unit 7 located at outside of the ODTS 1 operates in the self-refresh mode and changes a self-refresh period of the semiconductor memory device in response to the plurality of flag signals TRIP_POINT_FLAG<1:M>.
As described above, the conventional ODTS 1 can operate when the enable signal ENABLE, the self-refresh signal SREF, and the test enable signal TEST_ENABLE are input from the outside. It is debated in a Joint Electron Device Engineering Council (JEDEC) about a method for using an impedance matching command ZQCAL_CMD to define an operating point of the ODTS, i.e., a time when the enable signal ENABLE, the self-refresh signal SREF, and the test enable signal TEST_ENABLE are input from the outside.
If not the impedance matching command ZQCAL_CMD, various commands used in the semiconductor memory device can be used for defining an operating point of the ODTS. Further, vendors for manufacturing and offering the semiconductor memory device can suggest various opinions according to their own conditions and interests. However, it is difficult to define a specification of the ODTS by coping with the various opinions of the vendors one by one.